The present invention relates to a semiconductor device and a method of producing the same. Particularly, the invention relates to semiconductor device and production method of the a CMOS transistor pair composed of a P channel MOS transistor having a polysilicon gate and an N channel MOS transistor having a polysilicon gate. More specifically, the invention relates to the semiconductor device and production method of the same operable at a low voltage of about 1.5 V and at a high speed.
In the ordinary silicon gate technology, an N type polysilicon gate is doped with a great amount of phosphorus and a P type polysilicon gate is doped with a great amount of boron. These gates are formed on a silicon substrate or on an ion-implanted well layer in a silicon substrate. If the gate electrode material is utilized as a gate electrode of a MOS transistor, such as an N type polysilicon gate for an N channel MOS transistor, a work function difference is relatively great between the semiconductor substrate and the polysilicon so that a threshold voltage is lowered. Therefore, normally a channel region is ion-implanted with an impurity such as boron having the same electroconductivity type as that of the substrate, so as to regulatively raise the threshold voltage. On the other hand, if the gate electrode material is utilized as a different type of gate electrode material from a channel type of a MOS transistor such as N type polysilicon gate for a P channel MOS transistor, a work function difference is relatively small between the semiconductor substrate and the polysilicon gate electrode, hence the threshold voltage is negatively shifted. Therefore, in order to regulate an absolute value of the threshold voltage to a smaller level, an impurity such as boron having an opposite electroconductivity type to the semiconductor substrate is ion-implanted into the channel region of the substrate. Consequently, a P-N junction is formed. The former case is called a surface channel type device, and the later case is called a buried channel type device. The P channel MOS transistor and the N channel MOS transistor are coupled to one another to constitute a complementary pair, i.e., CMOS transistor pair.
In the CMOS technology, as the amount of boron doped into the channel region is increased, a threshold voltage of an N channel MOS transistor having the surface channel type is raised and a threshold voltage of a P channel MOS transistor having the buried channel type is lowered.
The semiconductor integrated circuit device containing a CMOS transistor pair as a basic element constitutes a CMOS IC which is suitable to, for example, use as a one chip microcomputer. Such a one chip microcomputer may be assembled into various portable and desk-top instruments, such as a controller. These portable and desk-top instruments normally utilize a battery as a power source. In view of compact design and power saving objectives, the instruments operate at a power source voltage of about 1.5 V supplied by a single dry cell battery. Consequently, it is one of the important targets of the art to lower an operation voltage of the CMOS IC.
In order to lower the operating voltage of the CMOS IC, it is necessary to reduce the threshold voltage of the MOS transistor. However, in case of lowering the threshold voltage of the CMOS transistor pair to, for example, 0.5 V which is needed for the 1.5 V operation, there is caused a problem in that a leak current of the MOS transistor increases. Therefore, electric charges in a battery are consumed rapidly even if the device using the battery is not operated. Hereinafter, this problem will be briefly discussed for better understanding of the background of the invention. AMOS transistor can be operated with currents flowing in an inverted channel region between a source region and a drain region by applying a voltage over the threshold voltage to a gate electrode and a constant voltage between the source region and the drain region. Although, as the threshold voltage being lowered, the channel region is inverted weakly, so that the currents flow between the source region and the drain region (leakage current). This mechanism will be explained by using FIG. 8 for better understanding. The curves in FIG. 8 are measurement data of drain current at the drain voltage V.sub.D =0.1 V. In this graph the horizontal axis represents a gate voltage V.sub.G and the normal axis represents a drain current I.sub.D in logarithmic scale. The curves show that the drain currents are not equal to OA at the gate voltage V.sub.G =0 V, therefore, the currents flow in the MOS transistor without operating the MOS transistor. In this an inversion value V.sub.G /log(I.sub.D) of an inclination of curve is named as a subthreshold coefficient S, which is an important value for determining a switching characteristic of the MOS transistor. A depletion layer capacity is formed just below the gate electrode in the surface of the MOS transistor. As the depletion layer capacity becomes greater, the subthreshold coefficient S becomes greater; on the contrary, as the depletion layer capacity becomes smaller, the subthreshold coefficient S becomes smaller. Further, the depletion layer capacity becomes large when the concentration of the substrate surface just below the gate electrode is high, while the depletion layer capacity becomes small when the concentration is low. Therefore, as the concentration of the substrate surface just below the gate electrode is lower, the depletion layer capacity becomes smaller, and the subthreshold coefficient S can be decreased. As a result, the MOS transistor can be operated with a narrow range of the voltage, and thereby it is possible to perform switching operation at high speed with a small consumption of electricity. Especially, in the P channel MOS transistor which is a buried channel type device, a comparatively large amount of boron is ion-implanted in order to keep the threshold voltage below 0.5 V, so that the concentration of the substrate surface is high. As mentioned before, a p-n junction is formed in a channel region of an n type well of the P channel MOS transistor having the N type polysilicon gate electrode and the buried channel. Thus, in the P channel MOS transistor, a level of the minimum potential does not exist at a boundary between a silicon substrate and a gate oxide film, but exists in an internal portion of the substrate to form a buried channel. As the p-n junction becomes deep, the level of the minimum potential shifts into the internal portion of the substrate to enhance a degree of the buried channel. Consequently, carriers in the buried channel are made free from surface scattering specific to the boundary to thereby increase mobility. As the amount of the ion-implanted boron increases to lower the threshold voltage, the p-n junction depth becomes deep to intensify the degree of the buried channel so that the mobility is raised.
In such a manner, the buried channel type device is advantageous, as compared to the surface channel type device, in that the mobility is much greater. However, the buried channel type device suffers from a most serious drawback in that a short channel effect is easily induced. This short channel effect causes secondary drawbacks such as increase in a leak current, degradation of a subthreshold characteristic and reduction in a punch-through breakdown voltage. In order to suppress such a short channel effect in the P channel MOS transistor of the buried channel type, the p-n junction depth must be set as shallow as possible, so that the P channel MOS transistor becomes closer to the surface channel type device. However, it is practically difficult to establish a quite shallow p-n junction depth. Conventionally, boron is ion-implanted to carry out the channel doping. A shallow diffusion layer cannot be formed because of relatively great diffusion coefficient of boron. Particularly, boron is ion-implaned by a great amount so as to suppress the threshold voltage at about 0.5 V, thereby rendering a deep p-n junction depth.
Aside from the above, in order to suppress the short channel effect of the P channel MOS transistor, it is known to form a surface channel type of the P channel MOS transistor like the N channel MOS transistor. Namely, an N type/P type bipolar gate structure is adopted instead of N type unipolar gate structure. In such a case, a P type polysilicon gate material is used as a gate electrode of the P channel MOS transistor. However, the N type/P type bipolar gate structure disadvantageously complicates not only fabrication process but also IC design. Particularly, a junction structure of lead lines is complicated to obtain an ohomic contact to opposite polarities of the gate electrodes, thereby disadvantageously enlarging IC chip size. In contrast, the N type unipolar gate structure has the advantages such as simple process and design and small chip size.